RISC V could anchor India’s national semiconductor mission: UST’s Gilroy Mathew
RISC‑V — an open, royalty-free instruction set architecture — could become the cornerstone of India Semiconductor Mission, according to UST’s COO Gilroy Mathew. He says India can leverage its strengths in chip design, software and backend engineering to build world-class RISC-V based chips, avoiding legacy infrastructure and accelerating the nation’s push for semiconductor self-reliance.
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